data bulletin MX609 1998 mx com, inc. www. mxcom.com tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20830064.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. an audio delay circuit based on the MX609 cvsd codec 1. introduction the schematic diagram shown on the following page is an audio delay circuit based on the MX609 cvsd codec. in addition to the MX609, the circuit uses a motorola mcm6287 64k x 1 bit ram, two 4520 counter ics, and a 4069 inverter chip. it provides up to two seconds of delay. this circuit provides a starting point for a designer who wishes to implement an audio delay circuit. mx-com makes no guarantee of its performance and assumes no responsibility for its use in any product. 2. circuit operation in the following operational description, a bar over a signal name is used to indicate an active low signal. for example, w is an active low write enable signal. on the MX609p, clock mode 1, pin 22, is tied to vdd and clock mode 2, pin 21, is tied to ground to set the encode and decoder clocks for a sampling rate of 32 kb/s. the encoder force idle, powersave, and decoder force idle inputs, pins 6, 15, and 16, respectively, are tied to v dd to set them inactive. the data enable input, pin 7, is tied to vdd to make the encoded data available at the encoder output, pin 5. pin 19, the algorithm select input, is tied to ground to select a four-bit companding algorithm. the other inputs are the same as recommended for external component connections shown in the mx-com data book. the audio signal to be delayed is input to pin 10 of the MX609, the encoder input, and is converted to a serial stream of digital data. the serial data are output on pin 5, the encoder output, and connected to pin 13, the d input, of the mcm6287 memory chip. the decoder data clock output from pin 18 of the MX609 is connected to pin 1 of the 4069 inverter. the output of the inverter, pin 2, is connected to pin 10 of the mcm6287, the w input, and to pin 3 of the 4069, the input to second inverter. pin 4, the inverter output, is connected to the enable input of the first 4520 counter. the enable input is taken from the second inverter to ensure that the 4520 counters increment after the w signal into the mcm6287 transitions from low to high. the clock inputs of each of the 4520s, pins 1 and 9, are tied to ground so that only the enable inputs control when the counters increment. the reset inputs, pins 7 and 15, are also tied to ground so that they never reset the counters. the individual four bit counters in the 4520s are cascaded to produce a 16 bit counter. the counter outputs, q15 - q0, are connected to the address inputs, a15 - a0, of the mcm6287. there are switches between q15 and a15 and between q14 and a14. the switches allow the number of bits of the counter, and therefore the length of the delay, to be adjusted. when the decoder data clock falls from high to low, the counter, and therefore the address, increments. since the w input to the memory, pin 17, is the complement of the clock, it rises from low to high, latching the encoded data bit at the d input. the e input to the mcm6287, pin 12, is tied to ground so that the memory is always selected. when w is high and the address is stable, a valid data bit appears at the q output, pin 17, of the mcm6287. the address of the data bit appearing at q is one greater than the address of the bit that was just written, so the counter must cycle through its entire range before a data bit that has been written into the memory can be read. therefore, a data bit output from the MX609 at the encoder output pin is delayed by the number of clock periods of the range of the counter. the delay is given by: delay = (t sec/cycle) * (2n cycles) where: t = period of decoder data clock n = number of bits used in counter if all 16 bits of the counter are used, and the decoder clock frequency is 32 khz, then the delay would be: delay: = (1/32000) sec/cycle * (216) cycles = 2.048 seconds
an audio delay circuit based on the MX609 cvsd codec application note 1998 mx com, inc. www. mxcom.com tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20830064.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. 2 in this example, all locations of the memory are used. if a shorter delay is desired, the switches connecting the counter outputs and address inputs can be opened. if only 14 bits of the counter are used, then the delay is reduced by a factor of four, to 0.512 seconds. the range of delays could be increased even more by adding more switches and by making the sampling clock frequency adjustable. the q output, pin 9, of the mcm6287 is connected to the decoder input, pin 17, of the MX609. the decoder clocks in the serial digital data stream from the memory and converts it to an analog signal, which is output at pin 13, the decoder output. the decoder output is the delayed audio signal. MX609p mcm6287 4520 4520 4069 4069 1 2 3 4 +5 +5 +5 +5 +5 100k 100k 10uf 1uf 1uf 1m 1.024 mhz 47pf 33pf audio signal output audio signal input 12 10 13 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 q vss vdd e w d 22 11 9 1 2 3 4 5 6 7 8 14 15 16 17 18 19 20 21 3 4 5 6 11 12 13 14 3 4 5 6 11 12 13 14 q1a q2a q3a q4a q1b q2b q3b q4b q1a q2a q3a q4a q1b q2b q3b q4b enb ena enb ena ca cb rsta rstb vss ca cb rsta rstb vss 1 9 7 15 8 1 9 7 15 8 10 2 10 2 16 16 vdd vdd 1 2 5 6 7 9 10 11 22 21 20 19 18 17 16 15 13 vdd clkmode1 clkmode2 algorithm dec data clock dec in dec force idle powersave dec out xtal xtal enc out enc force idle data enable bias enc input vss figure 1: audio delay circuit
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